Responsibilities:
· Lead full FPGA flow (ASIC emulation) from ASIC code to release of FPGA
platform for QA team.
· Responsible for multi-FPGA platform – simulation, synthesis, P&R and lab.
· Design FPGA specific blocks in verilog.
· Coordination between SW / HW / QA / VLSI teams.
Qualifications:
Years of Experience: 5+ years of experience in VLSI / FPGA design and in targeting design to FPGA Education: B.Sc. in Electrical Engineering
Requirements:
· Proficiency in Verilog / VHDL
· Proficiency in FPGA synthesis (Synplicity tools - Advantage)
· Proficiency in FPGA P&R (Altera Stratix – MUST)
Knowledge of Ethernet switching - Advantage